Espressif Systems /ESP32-C6 /EXTMEM /L1_CACHE_DATA_MEM_ACS_CONF

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Interpret as L1_CACHE_DATA_MEM_ACS_CONF

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (L1_ICACHE0_DATA_MEM_RD_EN)L1_ICACHE0_DATA_MEM_RD_EN 0 (L1_ICACHE0_DATA_MEM_WR_EN)L1_ICACHE0_DATA_MEM_WR_EN 0 (L1_ICACHE1_DATA_MEM_RD_EN)L1_ICACHE1_DATA_MEM_RD_EN 0 (L1_ICACHE1_DATA_MEM_WR_EN)L1_ICACHE1_DATA_MEM_WR_EN 0 (L1_ICACHE2_DATA_MEM_RD_EN)L1_ICACHE2_DATA_MEM_RD_EN 0 (L1_ICACHE2_DATA_MEM_WR_EN)L1_ICACHE2_DATA_MEM_WR_EN 0 (L1_ICACHE3_DATA_MEM_RD_EN)L1_ICACHE3_DATA_MEM_RD_EN 0 (L1_ICACHE3_DATA_MEM_WR_EN)L1_ICACHE3_DATA_MEM_WR_EN 0 (L1_CACHE_DATA_MEM_RD_EN)L1_CACHE_DATA_MEM_RD_EN 0 (L1_CACHE_DATA_MEM_WR_EN)L1_CACHE_DATA_MEM_WR_EN

Description

Cache data memory access configure register

Fields

L1_ICACHE0_DATA_MEM_RD_EN

The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable.

L1_ICACHE0_DATA_MEM_WR_EN

The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, 1: enable.

L1_ICACHE1_DATA_MEM_RD_EN

The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: enable.

L1_ICACHE1_DATA_MEM_WR_EN

The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, 1: enable.

L1_ICACHE2_DATA_MEM_RD_EN

Reserved

L1_ICACHE2_DATA_MEM_WR_EN

Reserved

L1_ICACHE3_DATA_MEM_RD_EN

Reserved

L1_ICACHE3_DATA_MEM_WR_EN

Reserved

L1_CACHE_DATA_MEM_RD_EN

The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: enable.

L1_CACHE_DATA_MEM_WR_EN

The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: enable.

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