Cache data memory access configure register
L1_ICACHE0_DATA_MEM_RD_EN | The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable. |
L1_ICACHE0_DATA_MEM_WR_EN | The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, 1: enable. |
L1_ICACHE1_DATA_MEM_RD_EN | The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: enable. |
L1_ICACHE1_DATA_MEM_WR_EN | The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, 1: enable. |
L1_ICACHE2_DATA_MEM_RD_EN | Reserved |
L1_ICACHE2_DATA_MEM_WR_EN | Reserved |
L1_ICACHE3_DATA_MEM_RD_EN | Reserved |
L1_ICACHE3_DATA_MEM_WR_EN | Reserved |
L1_CACHE_DATA_MEM_RD_EN | The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: enable. |
L1_CACHE_DATA_MEM_WR_EN | The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: enable. |